FPGA Based Implementation of Image Encryption Using Scan Patterns and Carrier Images
Yukthi.B.R1, Savitha.A.P2, M.B.Anandaraju3, Nuthan.A.C4
1Yukthi.B.R, PG Student, VLSI Design and Embedded System, B.G.S. Institute of Technology, B. G. Nagar, Mandya, Karnataka, India.
2Savitha.A.P, Associate Professor, Department of Electronics and Communication Engineering, B.G.S. Institute of Technology, B.G.Nagar, Mandya, Karnataka, India.
3M. B. Anandaraju, Professor and HOD, Department of Electronics and Communication Engineering, B.G.S. Institute of Technology, B.G.Nagar, Mandya, Karnataka, India.
4Nuthan.A.C, Assistant Professor, Department of Electronics and Communication Engineering, G. Madegowda Institute of Technology, Bharathinagara, Mandya, Karnataka, India.
Manuscript received on June 05, 2013. | Revised Manuscript received on June 11, 2013. | Manuscript published on June 15, 2013. | PP: 45-47 | Volume-1 Issue-7, June 2013. | Retrieval Number: G0342061713
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents an FPGA implementation of image encryption method using carrier images and scan patterns generated by scan methodology. The scan is a language-based two-dimensional spatial-accessing methodology which can efficiently specify and generate a wide range of scanning paths. Then scanning paths sequence fill in original image. The carrier image is created with the help of alphanumeric keyword. Each alphanumeric key will be having a unique 8bit value generated by 4 out of 8-code.This newly generated carrier image is added with the original image to obtain encrypted image. The scan methodology is applied to either original image or carrier image, after the addition of original image and carrier image to obtain the highly distorted encrypted image. By applying the reverse we get the decrypted image. Reversible logic is most popular concept in energy efficient computations and this will be demand for upcoming future computing technologies. The proposed paper will be simulated using Xilinx simulator and implemented in Xilinx FPGA platform.
Keywords: Carrier image, Encryption, Scan patterns, 4 out of 8-code.