Power Efficient Double Gate MOSFET Full Adder Circuit using 45nm Technology
Rajesh Kumar Panda1, Ralesh Ranjan Biswal2, Jyoti Sankar Sahoo3
1Mr. Rajesh Kumar Panda, Department of Electronics and Communication Engineering, KIIT University, Bhubaneswar, Odisha, India.
2Mr. Ralesh Ranjan Biswal, Department of Electronics and Communication Engineering, KIIT University, Bhubaneswar, Odisha, India.
3Jyoti Sankar Sahoo, Department of Electronics and Communication Engineering, KIIT University, Bhubaneswar, Odisha, India.
Manuscript received on April 30, 2015. | Revised Manuscript received on May 06, 2015. | Manuscript published on May 15, 2015. | PP: 47-51 | Volume-3 Issue-6, May 2015. | Retrieval Number: F0857053615/2015©BEIESP
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Abstract: In designing an arithmetic circuit many aspects are to be taken into consideration. The main aspect is the power consumption. It is a tough task for the designers to design a circuit which consume less power in standby mode as well as in active mode. In an arithmetic circuit, the adder is an important module not only for addition operation but it is also the nucleus for many arithmetic operations. Hence it is required to reduce the power consumption of adder circuit in order to reduce the power consumption of the arithmetic module. As the efficiency of adder circuit is directly influence the efficiency of the arithmetic circuit, therefore many designs have been proposed in various literatures to resolve this issue. The very promising and advanced design is to implement the full adder circuit with double gate MOSFET. As technology growing, the full adder is now implemented by using 10 number of double gate transistors instead of 28 transistors as in the peer CMOS design. But still the power consumption of this circuit is not appreciably reduced. In this paper we proposed a design which is made up of 10T double gate (DG) MOSFETs in which all the bodies of P-type Double Gate-MOSFETs are connected to a supply less than the main supply and all the bodies of N-type Double Gate-MOSFETs are connected to another supply voltage whose value is slightly greater than zero. In the earlier design the output is not prominently stated but in this proposed modified design the output waveform is clearly distinguished by adding extra buffers to the output. In this new proposed design the static or standby power is reduced nearby 93% and the total power is reduced nearby 79% as compared to the earlier design. Simulation results of the proposed modified design is performed by cadence virtuoso with 45nm technology for validation
Keywords: DG-MOSFET, 10T Full adder, Low power adder circuit.