Scalable Antirandom Testing (SAT)
Muhammad Sadiq Sahari1, Abu Khari A’ain2, Ian A. Grout3
1Muhammad Sadiq Sahari, PhD Student, Department of Microelectronics and Computer Engineering, Faculty of Electrical Engineering, Universiti Teknologi Malaysia.
2Abu Khari A’ain, Prof., Department of Microelectronics and Computer Engineering, Faculty of Electrical Engineering, Universiti Teknologi Malaysia.
3Ian A. Grout, Prof., Department of Electronics and Computer Engineering, University of Limerick.
Manuscript received on March 06, 2015. | Revised Manuscript received on March 11, 2015. | Manuscript published on March 15, 2015. | PP: 33-35 | Volume-3 Issue-4, March 2015. | Retrieval Number: D0820033415/2015©BEIESP
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© The Authors. Published By: Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Antirandom testing approach requires large input space and complex test vector generation algorithm when used on circuit under test (CUT) with large number of inputs. In this work, we proposed a novel and simple approach of Antirandom sequence generation by using the least significant bit (LSB) of the test vector as a reference to generate the next test vector. Fault simulations on ISCAS’85 benchmark circuits shown that a high fault coverage for combinational logic circuits has been obtained. Another attractive feature of the proposed technique is the scalable of the algorithm that can be generate test vectors in short time even for CUT with large number of inputs.
Keywords: Integrated Circuit (IC) Testing, Built-in self-test (BIST), Test Pattern Generation (TPG), Pseudorandom Testing and Antirandom Testing.